Noise Reduction in Transistor Oscillators
Optimization of low frequency loading and feedback circuit can help minimize the 1/f noise in the transistor oscillators. In a first approximation, a gate voltage noise generator connected in series with a noise-free nonlinear two-port circuit can model the low frequency 1/f noise in FET devices. So, if the low-frequency voltages applied to gate-source and drain-source terminals are reduced, the resulting sideband components around the oscillation frequency due to nonlinear mixing of these voltages will be reduced as well. To realize such an approach, it is necessary to provide the short-circuiting of the drain port and open-circuiting of the gate port at low frequencies . The phase noise improvement under these conditions was verified experimentally by connecting external variable resistances Rg and Rd to the gate and drain ports, as shown in Figure 13(a), where Cb are the blocking capacitances. The minimum phase noise conditions are realized for ideal case when Rg = ∞ and Rd = 0. This means that, in practice, a high value of external resistance Rg at low frequencies is needed when it is bypassed by the choke inductance Lch, and no converted noise variations will be observed. It was found that 1/f noise could be approximated by a quasi-stationary phenomenon having a quasi-constant autocorrelation function