Methodology on Extracting Compact Layout Rules for Latchup Prevention in Deep Submicron Bulk CMOS Technology
An experimental methodology to find area-efficient compact layout rules to prevent latchup in bulk complimentary metal–oxide–semiconductor (CMOS) integrated circuits (ICs) is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new latchup prevention design by adding the additional internal double guard rings between input/output cells and internal circuits is first reported in the literature, and its effectiveness has been successfully proven in three different bulk CMOS processes. Through detailed experimental verification including temperature effect, the proposed methodology to extract compact layout rules has been established to save silicon area of CMOS ICs but still to have high enough latchup immunity. This proposed methodology has been successfully verified in a 0.5- m nonsilicided, a 0.35- m silicided, and a 0.25- m silicided shallow-trench-isolation bulk CMOS processes. LATCHUP in bulk complimentary metal–oxide–semiconductor (CMOS) integrated circuits (ICs) is formed by the parasitic p–n–p–n structure between and of CMOS circuits [1]–[3]. This parasitic structure inherently exists in the bulk CMOS technology. When the parasitic p–n–p–n structure is triggered to cause latchup, it generates a low-impedance path from to and a high current to often burn out the chip. The device cross-sectional view of a latchup path in a p-substrate bulk CMOS technology is shown in Fig. 1(a), where the first-order equivalent circuit of a latchup path is illustrated in Fig. 1(b). The latchup equivalent circuit is formed by a vertical p–n–p bipolar junction transistor (BJT) (Qpnp) coupled with a lateral n–p–n BJT (Qnpn). When one of the BJTs is turned on, the mechanism of positive feedback regeneration in the latchup structure will be initiated [4], [5]. If the product of beta gains of these two BJTs can be kept Fig. 1. (a) Device cross-sectional view and (b) equivalent circuit of latchup structure in a p-substrate bulk CMOS technology. greater than one, the p–n–p–n structure will hold in a stable latching state . To prevent the occurrence of latchup in CMOS ICs, some advanced process technologies (such as the epitaxial substrate , retrograde well , trench isolation , or silicon-on-insulator) have been reported to increase holding voltage of the parasitic p–n–p–n structures. Although such advanced techniques can effectively solve the latchup issue in CMOS ICs, the production cost of CMOS ICs with such advanced techniques becomes more expensive. Thus, the most consumer IC products are still manufactured by bulk CMOS processes. In the bulk CMOS processes, the latchup issue is mainly prevented by guard rings which have been specially specified in the design rules of a CMOS process. The wider guard rings used to surround the input/output (I/O) devices in I/O cells of CMOS ICs generally cause a higher latchup immunity, but they also occupy a larger layout area