cadence assura tutorial 2
Introduction to Assura Physical Verification
Assura Physical Verification Tool Suite
Assura Task and Data Flow
- Viewing and Interpreting Graphical Results
- Viewing Assura Output Text Files
- Assura Internal Output Files
- Converting Assura Netlists to ASCII
- Converting the Layout Netlist to SPICE Format
- Assura Run-Time Environments
- Assura Installation Overview
- Running Assura Tools From the DFII GUI
- Running Assura in Standalone Graphical Mode
- Running Assura in Batch Mode from the UNIX Command Line
- Running the Assura Tool Using Remote Job Submission
- Creating the Preferences File for Running a Remote Job
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Assura Menu Overview
- Open Run…
- Open Cell…
- Technology…
- Rule Sets…
- Setup
- Run DRC…
- Run altPSM…
- Run LVS…
- Open ELW…
- Open VLW…
- LVS Debug Env…
- View Netlist…/Open Schematic Cell…
- LVS Error Report…
- Probing…
- Short Locator…
- MSPS…
- Run RCX…
- Close Run
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Assura DRC and LVS Run-time Options
Introduction
Specifying Inputs
- Input Settings for Assura DRC and LVS
- Input Settings for Assura DRC Only
- Input Settings for Comparing Two Layouts
- Input Settings for Assura LVS Only
- Input Settings for LVS and RCX
- Input Settings for RCX Only
Controlling Computing Resources
Using the Assura GUI to Set Run-time Options
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DRC Graphical User Interface Run Guide
- Buttons on Top of the Run Assura DRC Form
- Design to be Checked
- Run Name and Run Directory
- View Rules File and Rule Set
- View avParameters
- View Additional Functions
Hiding Individual Errors in the Design
- Error Corrections
- Error Signoffs
- Exception File
- Exception File Format
- Making Error Layers Visible or Invisible in the Design
- Zooming, Descending, and Editing in Place
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Viewing and Correcting DRC Errors
Steps for Viewing DRC Errors
Set up the VLW, Design Layout Window, and ELW
Select Error Layers
Select the Cell
- Using the Assura DRC Error Report
- Interpreting the Assura DRC Error Report
- Assura DRC Error Environments
Display the Error in a Graphics Window
Display Information About Shapes
Display the Summary Report
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Comparing Layout and Schematic Netlists
Directing the LVS Run with Compare Rules
- Controlling the Run
- Specifying the Input Netlists
- Specifying Devices
- Specifying Cells
- Specifying Nets
- Specifying Correspondence between Schematic and Layout
- Specifying Device and Circuit Reduction
- Specifying Device and Circuit Symmetry
- Comparing Parameters
- Controlling the Output Information
- Processing the Hierarchy
- Combining and Permuting MOS Devices
- Net Preprocessing
- Checking Preprocessing Results
- Specifying Cells for Automatic Pin Swap
- Limiting Automatic Pin Swapping to Unbound Pins Only
- Generating Swap Expressions
- Specifying Cell Hierarchies for Swap Analysis
- Interaction between autoPinSwap and Other Rules
- Using the fix Property in DFII
Optimizing LVS Runtime and Results
- Optimize the Layout
- How to Avoid Pin Problems
- How to Avoid Device-Climbing Problems
- How to Avoid and Fix LVS Mismatches with the Binding File
- Speed Up Pin Swapping
- Expand Cells with Errors
Using Block LVS Techniques
Using Black Box LVS Techniques
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LVS Graphical User Interface Run Guide
- Menu Bar
- Schematic and Layout Format Information
- Run Information
- View Rules Files
- Viewing and Modifying avParameters
- Viewing and Modifying avCompare Rules
- Viewing Additional Functions
- Open Run…
- Open Cell…
- LVS Debug Env…
- View Netlist…/Open Schematic Cell…
- LVS Error Report…
- Probing…
- Short Locator…
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Reconciling Layout and Schematic Mismatches
LVS Outputs
Checking the Summary Report
Checking Label Connectivity
Checking the LVS Report
- LVS Report Structure
- Statistics Section
- Instance Pin Errors Section
- Bad Initial Net Bindings Section
- Bad Net Matches Section
- Pin Errors Section
- Unmatched Internal Nets Section
- Problem Nets Section
- Suggested Terminal Rewire Section
- Bad Net Connections Section
- Unmatched Instances Section
- Unmatched Net Details Section
- Open Internal Nets Section
- Shorted Internal Nets Section
- Derived Instances Section
Interpreting the LVS Error Report
- Debugging Connection Problems
- Debugging Pin-Swapping Problems
- Expanding Cells with Errors
- Determining that Hierarchies Do Not Match
- Accounting for Device Climbing
- Verifying an Unfamiliar Layout
- Troubleshooting Special Problems
9
RCX Graphical User Interface Run Guide
RCX/RCX-FS Extraction Matrix
Assura RCX Overview
- Assura RCX Extraction Options
- Assura RCX GUI Features and Options
- How Assura RCX fits in the Assura Physical Verification Flow
How to Access the Assura RCX GUI
- Technology Selector and Rule Sets
- Using Multiple Rule Sets
- Output Format
- Spice Output
- Spectre Output
- Spice / Spectre Options
- Extracted View Output
- LVS Extracted View Output
- Cell-level DSPF Output
- Cell-level SPEF Output
- Transistor-level DSPF Output
- Transistor-level SPEF Output
- Resistance
- Capacitance
- Inductance
- RCX Extraction Modes
- How to Input Net Names
- RCX-FS Capacitance Extraction
- Hierarchical RCX
Filtering Options Tab
Netlisting Options Tab
Run Details Tab
Substrate Tab
The Assura RCX Run-Specific File
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Substrate Extraction
Introduction
Setup Substrate Extraction
Substrate Extract Tab
Log Files
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Outputting Your Data
- Layout Editing or Viewing Flow (Backward Recombination)
- Database Merge Using Different Modes
- eraseLayer
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Assura Run-time Resource Allocation
Using Multiple Disks
Using Multiple Processors
A
Virtuoso Phase Designer
Key Product Features and Dependencies
Key Steps in PSM Layout Creation