basic knowledge for a layout designer
The layout engineer should have
• Detailed knowledge of the entire set of layers and layout design rules.
• The size of the design, estimated from the number of transistors in the design
and the layout design rules.
• Attention to transistor-level placement and interconnect to implement
logic gates.
• Careful floorplanning and architecture definition to minimize area and maximize
performance. These leaf cells are potentially used thousands of times,
so the extra effort in achieving area savings for each cell is justly rewarded
in the finished chip.
• Careful design of the power supply implementation. This also includes
consideration of substrate and tub contacts. If this is done well, the power
supply routing and bulk connection requirements of an entire block or chip
can be met by building these requirements into the design of the leaf cells.
• Attention to the design of the interface to other cells. As mentioned previously,
these leaf cells may be used many, many times, and area savings can
be achieved by minimizing the overhead required to place two leaf cells adjacent
to each other. Ideally, leaf cells should be designed to abut directly to
all possible cells that may be placed adjacent to them.