vlsi techniques-Asynchronous Reset
An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter what the clock signal is. This is considered as high priority signal and system reset happens as soon as the reset assertion is detected.
Advantages:
High speeds can be achieved, as the data path is independent of reset signal.
Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present.
As in synchronous reset, no work around is required for logic synthesis.
Disadvantages:
The problem with this type of reset occurs at logic de-assertion rather than at assertion like in synchronous circuits. If the asynchronous reset is released (reset release or reset removal) at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable.
Spurious resets can happen due to reset signal glitches.