vlsi interview question-objective type-07



111 Data Warehousing refers to (a) storing data offline at a separate site (b) backing up data
regularly (c) is related to data mining (d) uses tape as opposed to disk
112. A 4GL is (a) DBMS system (b) uses Java (c) uses C++ (d) none of the previous.
113. The Pentium processor is (a) 16-bit (b) 32-bit (c) 64 bit (d) 8-bit
114. The IBM/Motorola PowerPC 601 processor is (a) 16-bit (b) 32-bit (c) 64 bit (d) 8-bit
115. The Motorola 68000 processor is (a) 16-bit (b) 32-bit (c) 64 bit (d) 8-bit
116. The Digital Alpha processor is (a) 16-bit (b) 32-bit (c) 64 bit (d) 8-bit
117. Apple’s iMac uses a (a) ISA bus (b) NuBus (c) PCI bus (d) USB bus
118 Which of the following is NOT a bus standard (a) EISA (b) VME (c) MCA (d) RS-232
119. A nanosecond is (a) 10
– 6
sec (b) 10
– 3
sec (c) 10
– 1 2
sec (d) 10
– 9
sec
120. The feature size of a Pentium is approx. (a) 1 micron (b) 0.1 microns (c) 4 microns
(d) .4 microns
121. The resolution of an SVGA screen is (a) 1024 x 768 (b) 512 x 512 (c) 640 x 480 (d)
800 x 800
122. A 5 stage pipeline with the stages taking 1, 1, 3, 1, 1, units of time has a throughput of (a) 1/3 (b) 1/7 (c) 7
(d) 3
123. Given a 5 stage pipeline with stages taking 1, 2, 3, 2, 1 units of time, the throughput of the pipeline is:
(a) 9 (b) 1/9 (c) 1/3 (d) 2
124. Given a 5 stage pipeline with stages taking 1, 2, 3, 1, 1 units of time, the clock period of the pipeline is:
(a) 8 (b) 1/8 (c) 1/3 (d) 3
125. Given a 5 stage pipeline with stages taking 1, 2, 3, 1, 1 units of time, the flowthrough time of the pipeline is:
(a) 8 (b) 1/8 (c) 1/3 (d) 3
126. The average memory access time for a machine with a cache hit rate of 90% where the cache access time is
10ns and the memory access time is 100ns is (a) 55ns, (b) 45ns, (c) 90ns, (d) 19ns77
127. The clock speed of a modern PC is of the order of (a) 400 Khz (b) 400 Hz (c) 400
Mhz (c) 400 Ghz
128. Given that the subprogram putc displays the character in al, the effect of the following instructions:
mov al, ‘c’
sub al, 2
call putc
is to (a) display 2 (b) display ‘c’ (c) display ‘a’ (d) display a blank
129. Given that the bl register contains ‘b’, the effect of the following instruction
and bl, 1101 1111
is to (a) clear bl (b) store ‘B’ in bl (c) store 0010 0000 in bl (d) leave bl unchanged
130. Which of the following is an illegal instruction
(a) MoV Ax, 30000 (b) iNc Al, 1 (c) aNd bx, bx (d) add ax, 30