Simulation of High Speed Interconnects
With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects, such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper, various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail.
The recent trend in the VLSI industry toward miniature designs, low power consumption, and increased integration of analog circuits with digital blocks has made the signal integrity analysis a challenging task. The quest for high-speed applications has highlighted the previously negligible effects of interconnects (Fig. 1), such as ringing, signal delay, distortion, reflections, and crosstalk. Interconnects can exist at various levels of design hierarchy (Fig. 2) such as on-chip, packaging structures, multichip modules, printed circuit boards, and backplanes. It is predicted that interconnects will be responsible for majority of signal degradation in high-speed systems High-speed interconnect problems are not always handled appropriately by conventional circuit simulators, such as SPICE [23]. If not considered during the design stage, these interconnect effects can cause logic glitches that render a fabricated digital circuit inoperable or they can distort an analog signal such that it fails to meet specifications. Since extra iterations in the design cycle are costly, accurate prediction of these effects is a necessity in high-speed designs. Hence, it becomes extremely important for designers to simulate the entire design along with interconnect subcircuits as efficiently as possible while retaining the accuracy of simulation [23]–[139]. A. What is High-Speed? Speaking on a broader perspective, a “high-speed interconnect” is the one in which the time taken by the propagating signal to travel between its end points cannot be neglected. An obvious factor that influences this definition is the physical extent of the interconnect; the longer the interconnect, the more time the signal takes to travel between its end points. Smoothness of signal propagation suffers once the line becomes long enough for the signal’s rise/fall times to roughly match its propagation time through the line. Then the interconnect electrically isolates the driver from the receivers, which no longer function directly as loads to the driver. Instead, within the time of the signal’s transition between its high and low voltage levels, the impedance of interconnect becomes the load for the driver and also the input impedance to the receivers [1]–[12]. This leads to various transmission line effects, such as reflections, overshoot, undershoot, crosstalk, and modeling of these needs the blending of EM and circuit theory. Alternatively, the term “high-speed” can be defined in terms of the frequency content of the signal. At low frequencies an ordinary wire, in other words, an interconnect, will effectively short two connected circuits. However, this is not the case at higher frequencies. The same wire, which is so effective at lower frequencies for connection purposes, has too much inductive/capacitive effects to function as a short at higher frequencies. Faster clock speeds and sharper slew rates tend to add more and more high-frequency contents.