sample and hold model
sample and hold model
sampler model show the application of the sample&hold model with the clock generator
// samle_hold model:
// The sampling model is triggered by the clock. At every falling edge
// of the clock the input voltage is measured and stored in an intermediate
// variable. As long the clock is zero, the measured value is applied to
// the output node. If the clock goes to high, the voltage at the input
// node is passed through to the output node.
module sample_hold(in,out,clk);
input in,clk;
output out;
voltage in,out,clk;
parameter real slewrate = 1.0e-9 from (0:inf);
parameter real clk_vth = 2.5;
real v;
analog
begin
if (analysis(“static”) || (V(clk) > clk_vth))
v = V(in); // passing phase
@(cross(V(clk)-clk_vth,-1))
v = V(in); // sampling phase
V(out) <+ slew(v,slewrate);
end
endmodule
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// sampler:
// Hierarchical connection of the clock generator and sample_hold model
// to describe a sample&hold circuit.
//
module sampler(in,out)
input in;
output out
voltage in,out;
parameter real clk_period = 5n from (0:inf);
parameter real slewrate = 1.0n from (0:inf);
parameter real clk_high = 5.0;
parameter real clk_low = 0.0 from (-inf:clk_high);
clock_generator #(clk_period,clk_high,clk_low)
clock(clk);
sample_hold #(slewrate,(clk_high-clk_low)/2)
S_H(in,out,clk);
endmodule