rfic testing
The fabrication of RFIC’s requires the integration of several components onto a single board. The main component is the MMIC, which includes most of the active circuitry. Surface mount components (SMTs) are also used for tuning and to provide bypassing of the bias networks. Bond wires and microstrip lines are used as interconnects. Due to this complexity, multiple inter-operable simulation platforms are required to design and model these circuits. Unfortunately, the prototype or test board design is often an afterthought and is prone to effects such as over-moding due to the presence of CPW, slotline, and microstrip propagation modes. In addition, other effects such as coupling and parasitic inductance and capacitance due to bond wires and solder pads must also be considered. Sonnet is a powerful EM simulation tool that can be used in the design of design test boards. Sonnet allows internal ports to be included which are then used in a standard circuit simulator to include effects of SMTs, bond wires, and the MMICs. This is advantageous in that the designer can layout a test board, EM simulate it, and then optimize the SMT values for optimum performance. This procedure can be carried out using only one or two EM simulations of the test board and is similar to tuning methods . Sonnet uses co-calibrated ports in the interior of the circuit. During the simulations, these ports are de-embedded so that the coupling between the ports is removed. This allows for external components like chip inductors, capacitors, and resistors to be connected to the circuit outside of the Sonnet environment. This is useful in the test board design because it allows a wide range of SMTs having different values from different vendors to be considered in the test board design. Test board design can be easily over-constrained in that the SMTs, MMIC die, bond wires must all be accommodated. As a result, the effects of parasitics and coupling can result in unwanted resonances. These effects cannot always be detected using the built-in or “canned” models in circuit simulators