Power Dissipation in CMOS Technology
The VLSI low power design problems can be broadly classified into two analysis and optimization. Analysis problems are concerned about the accurate estimation of the power or energy dissipation at different phases of the design process. The analysis techniques differ in their accuracy and efficiency. Analysis technique also serves as the foundation for design optimization. Optimization is the process of generating the best design, given on optimization goal, with out violating design specifications. have proposed several heuristics both for combinational circuits and scan1based sequential circuits. They show that computing an optimal order of the test vectors such that the switching activity of a combinational circuit is minimized is an NP1hard problem. There are two types of power dissipation in CMOS circuits.
1. Dynamic power dissipation
2. Static power dissipation
Dynamic power dissipation is caused by switching activities of the circuit. A higher operating frequency leads to more frequent switching activities in the circuit and results in increased power dissipation . Static power dissipation is related to the logical states of the circuits rather than switching activities, in CMOS logic, leakage current is the only source of static power dissipation. However, occasional deviations from the strict CMOS style logic can cause static current to be drawn.