phase locked loop
Phase-Locked Loop (PLL) circuits are used for frequency control.The circuit operation isbasically a feedback system that controls the phase of a voltage-controlled oscillator (VCO).
The input signal is applied to one phase detector input. The other input is connected to a divide-by-N counter output. Normally the frequencies of both signals will be nearly the same. The phase detector output is a voltage proportional to the phase difference between the two inputs. This signal is applied to the loop filter. The loop filter determines the PLL’s dynamic characteristics. The filtered signal controls the VCO. Note that the VCO output is at a frequency that is N times the input supplied to the frequency reference input. This output signal is sent back to the phase detector via the divide-by-N counter.
Normally, the loop filter is designed to match the characteristics required by the PLL’s application. If the PLL is to acquire and track a signal, the loop filter bandwidth will be greater than if it expects a fixed-input frequency. The frequency range which the PLL will accept and lock on is called the capture range. Once the PLL is locked and tracking a signal, the range of frequencies the PLL will follow is called the tracking range. Generally, the tracking range is larger than the capture range. The loop filter also determines how fast the signal frequency can change and still maintain lock. This is the maximum slewing rate. The narrower the loop filter bandwidth, the smaller the achievable phase error. This comes at the expense of slower response and reduced capture range.
PLL and Clock Recovery
Circuits
A Sub-psec Jitter PLL for Clock Generation in 0.12µm Digital CMOS
A 10-Gb/s Clock Recovery Circuit with Linear Phase Detector and Coupled Two-stage Ring Oscillator
Low-Voltage CMOS Charge-Pump PLL Architecture for Low Jitter
Operation
A 100MHz, 8mW ROM-Less Quadrature Direct Digital Frequency Synthesizer
RF Receivers and Transmitters
A 35-mW – 3.6mm2 Fully Integrated 0.18µm CMOS GPS Radio
Fully Integrated Zero IF Transceiver for GPRS/GSM/DCS/PCS Application
A Direct Conversion CMOS Receiver Front-End with on-chip LO for UMTS
A Highly Integrated Si/SiGe BiCMOS Upconverter RFIC For 3G WCDMA Handset Applications
PLL Fundamentals application note from motorolla
PLL modeling and simulation ; designers-guide.com
Software for PLL Design
National’s PLL Design Software
Digital Phase Locked Loop Design
Mathcad routines for PLL Analysis
3rd order PLL design ; online application
Simulink ; communication system toolbox
Spurs and Phase Noise
Techniques for Measuring Phase Noise