Modeling tools for SOC design
• VHDL and Verilog are the two most popular and widely used hardware
description languages. They are well suited for modeling hardware, and the
accompanying synthesis tools are mature and produce optimized hardware. But,
the drawback is that neither language has suitable constructs for high-level
system modeling. They also do not support hardware-software co-modeling and
co-simulation, and they are very poor in modeling software constructs. Other
limitations of VHDL and Verilog include poor simulation speed and efficiency,
and the inability to incorporate existing C/C++ IP which has been tested,
debugged, and optimized into designs.
There is a need for a modeling language that can scale from high-level abstract modeling
to low-level RTL modeling. Some of the new languages that fall into this category are
SystemC, Cynlib, and Superlog.
SystemC is a C++ class library for modeling system level designs. SystemC is
primarily targeted towards modeling of complex System On Chip (SOC) designs. It is an
industry-sponsored open standard for system-level modeling platforms. Since SystemC is
based on C++ classes, it inherently supports the modeling of software. It also has classes
to model hardware constructs such as signals and ports. SystemC has a built in simulation
kernel. A general purpose C++ compiler can used to compile the SystemC model. The
output of the compiler is an executable file, which upon execution simulates the model.
Models can be developed and debugged using general tools such Visual Studio or GNU’s
gcc/gdb. SystemC models can output trace files that are compatible with standard
waveform display tools.
Cynlib is also based on a C++ class library . It is a set of C++ classes which
implement features necessary for modeling hardware. The library creates a C++
environment in which both the hardware and the test environment can be modeled and
simulated. However, the focus of Cynlib is more towards hardware modeling in C++
rather than system-level modeling.
Superlog is an extension of Verilog with support for C language features. It is not
compatible with general C/C++ compilers and needs its own set of tools for simulation.