high speed divider



By comparison, the conventional programmable divider consists of a dual-modulus prescaler (DMP), a program (P) counter and a swallow (S) counter and is depicted in the block diagram shown in Figure 1. A DMP is used to get higher resolution. A DMP allows the prescaling factor to be changed between N and N+1. Prescaler divides 2.4 GHz down to the 75 MHz, which is used for the following loadable counters to minimize the silicon area and power. Here, a program counter acts as coarse tuner and a swallow counter as fine tuner. The counter/divider M is given as:
M = (N+1) S + N (P – S) = NP + S
For proper functioning of the counters, S should be smaller than P and S must also be less than N. The numbers of N, P and S should be chosen carefully according to the maximum limitation of the allowable input frequency of the counters.
The conventional design has the following issues:
Requires two loadable down-counters.
Reduces speed, due to delay introduced in the counter path.
Increases design complexity while designing the loadable flip-flops.
Reduces robustness of the circuit.
Offers high power consumption at ~24 mW.
Increases hardware and silicon area.
Proposed programmable divider
The proposed programmable divider consists of a dual-modulus prescaler (DMP), an up-counter, an equality detector, an analog MUX and PCFR logic. The conceptual diagram is shown in Figure 2.
In Figure 2, Fin = sinusoidal input frequency, Fout = output frequency, CR = coarse register, FR = fine register and PCFR logic = prescaler, coarse, fine selector and reset generation block. Now the formula for the proposed programmable divider is:
M = {( N * CR ) + ( FR * 2 )}
The DMP divides sinusoidal input signal by either N or N+1. That is, DMP will perform divide-by-32; when MC = 0, and divide-by-33; when MC = 1. Thus, the input frequency is divided down to 75.375 MHz, 77.625 MHz from 2.412 GHz, 2.484 GHz respectively for MC = 0. The up-counter block operates with this downed frequency. The up-counter is itself a programmable frequency divider whose function is to increment the counter output on the rising edge of the downed frequency (CLK) and reset the counter output asynchronously when reset = 1.
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Design of high-speed, low-power frequency dividers and phase … we have compared the performance of the proposed divider. topology with that of two high-speed dividers reported in [5]. and [6]. Plotted … DESIGN OF HIGH-SPEED, LOW-POWER FREQUENCY DIVIDERS. 105. (c). Fig. 10. Continued (c) fin = 13:4 GHz (input amplitude not to scale). Fig. 11. Measured … input termination, the same arrangement as the divider has. been used. The circuit has been tested on wafer using high-. speed Picoprobes to apply the input and sense the output …
http://www.ee.ucla.edu/~brweb/papers/Journals/BRFeb95.pdf
A 13.4-GHz CMOS frequency divider Thus, high-speed divider topologies using stacked devices or. pass gates do not necessarily achieve a higher speed if they. incorporate this structure. Another … dividers reported in 111 and [51. Plotted in Figure 3 is the. pare performance of the proposed topology wilh high-speed … Since the primary goal is high speed, all devices. are ring-shaped and hence have a minimum width of 10pm. Forclockfrequenciesbelow lOGHz, a design employingsmaller …
http:www.ee.ucla.edu/~brweb/papers/Conferences/R&Y94.pdf http://www.ee.ucla.edu/~brweb/papers/Journals/BRFeb95.pdf
[PDF] A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider File Format: PDF/Adobe Acrobat – Quick View flip-flop-based frequency divider incorporating a new high-speed. latch topology, which provides satisfactory performance for. frequencies up to 17 GHz. This … This works explores the extension of flip-flop-based dividers to. higher frequencies by introducing novel high-speed latch topologies. … 3, that lead to a complete operation failure at very high speed data-. rates (> 10Gbit/sec). Fig. 2. Flip-flop based divider operation …
http:www.ece.uci.edu/~payam/FF_Divider_ISCAS04.pdf http://www.ee.ucla.edu/~brweb/papers/Journals/BRFeb95.pdf
[PDF] IMPLEMENTATION OF A PROGRAMMABLE HIGH SPEED DIVIDER FOR A 2.4 GHZ … The design of a programmable high speed divider for a RF Frequency Synthesizer using CMOS 0.35 µm technology (four. metal levels and 2 poly levels) is presented. The … grammable high speed divider reaches a maximum frequency of 2.75 GHz and power consumption of 5.6 mW with 3.3V … The design of a programmable high speed divider using a. 0.35 µm CMOS process (see Table 1 for the process details). is presented in this work. The divider has a dual modulus …
http:www.iberchip.org
The Care and Feeding of High Speed Dividers High speed divider applications require the printed circuit. boards to be mechanically designed with two considerations. in mind: (1) Electrical performance … Circuit design and layout for high speed dividers operating at frequencies up to 5GHz owe much more to analog RF. design techniques than normal digital ones and the … The input impedance of SP8000-series high speed dividers. varies as a function of frequency and is therefore specified on …
http:www.zarlink.com/zarlink/an178-appnote.pdf