frequency divider
Introduction In the wireless communication market, trends are moving towards smaller size, fewer parts, longer lifetime and higher frequency operation. These trends imply that wireless communications circuits must incorporate higher integration and that their design and IC technology must be optimized for low power and high frequency system. One innovative method to increase the frequency of programmable divider is discussed. The new method not only increases the frequency of operation but also decreases circuit complexity and power dissipation. This new design use synchronous counters instead of asynchronous counters. The digital gates are optimized for minimum propagation delay and loading effect using progressive sizing of the transistors. This is better configuration in every aspect in terms of frequency, power dissipation and chip area. The scaling of CMOS technologies to deep submicron has made CMOS a technological option for the low-gigahertz frequency range. However, for CMOS to become a commercial option for RF building blocks requires compliance to all trends of the consumer market: miniaturization, low cost, high reliability and long battery lifetime. Bulk CMOS technologies presently available satisfy the low cost and reliability trends by standard design practice. Complying with miniaturization and long battery lifetime, on the other hand, demands CMOS building blocks with low-power dissipation and good electromagnetic compatibility (EMC) characteristics. A critical RF function in this context is the frequency synthesizer, more particularly the programmable frequency divider. The divider consists of logic gates Which operate at RF frequency, Due to the divider’s complexity, high operation frequency normally leads to high power dissipation. Other crucial aspects of the present-day consumer electronics industry are the short time available for the introduction of new products in the market, and the short product lifetime. On top of that, the lifespan of a given CMOS technology is also short, due to the aggressive scaling of minimum feature sizes. Short time-to-market demands architectures providing easy optimization of power dissipation, fast design time and simple layout work. High reusability, in turn, requires an architecture, which provides easy adaptation of the input frequency range and of the maximum and minimum division ratios of existing designs. The choice of the divider architecture is therefore essential for achieving low-power dissipation, high design flexibility and high reusability of existing building blocks. The divider can be implemented using static or dynamic cmos circuits. Dynamic circuit techniques evolved in the last few years into several cmos circuit technique such as domino, NORA, TSPC circuits. Nevertheless, the field of CMOS integrated circuits has reached a level of maturity, where it is now mainstream technology for higher integration density, low power consumption. Therefore, we had chosen cmos to design the programmable divider. The designed dividers have increased frequency capability with reduction of propagation delay using synchronous counters instead of asynchronous counters. visit http://www.suchitav.com for download articles
Design
frequency divider is an important building block in today’s TRFIC and microwave circuits because it is an integral part of thephase-locked loop (PLL) circuit. In a typical PLL loop, the output ofthe voltage-controlled oscillator (VCO) is divided down by the frequencydivider to a frequency the temperature-compensated crystaloscillator (TCXO) operates (typically from 10 MHz to 30 MHz). Thedivided signal and TCXO are fed into the phase detector for comparison.The output phase difference is used to adjust the VCO outputfrequency. The frequency divider is also widely used to generate aprecision I/Q signal if the input signal has a 50% duty cycle, for themodern in-phase and quadrature (I/Q) modulator or demodulator.For the signal with duty cycle other than 50%, an additional divideby-2 can be used to generate the 50% duty cycle. Compared with thetraditional resistor and capacitor (RC) quadrature generation, thefrequency divider approach is easier to implement, is lower powerand offers smaller phase imbalance.
Digital logic approaches Since the PLL is part of the RF circuit, one would think thefrequency divider should be analyzed by the analog circuit theory.But it turns out the most widely used approach is based on the digitallogic gate. The RF analog engineer typically puts on the digital logichat for a minute when analyzing the frequency divider. It will be mucheasier to understand and analyze the digital approach in the digitaldomain and the analog approach in the analog domain. Within thedigital domain, the design strategy can be further divided into twocategories: static logic and dynamic logic.The static implementation is the most popular approach. Thememory cell is a true bistable circuit, unlike the parasitic capacitorused in the dynamic approach. One standard design is the divider by2 cell shown in Figure 1. In today’s design software, it is treated as astandard digital cell. There are many names for circuits similar toFigure 1, such as a Johnson divider, toggle switch, complementarymetal oxide semiconductor (CMOS) prescaler, emitter couple logic(ECL) and a source couple logic (SCL). When it is implemented inCMOS, it is called SCL. When it is implemented in a bipolar process,it is logically called ECL. For this illustration, CMOS implementation(SCL) is used.Free download the full document athttp://rfdesign.com/mag/503rfdf1.pdf
Analog approach The frequency divider with analog approach is also widely used. Ittends to be used in the very high frequency millimeter wave range,anywhere from 20 GHz up to 100 GHz. Also, they tend to be indiscrete form. The reason for this is the CMOS or BiCMOS processstill doesn’t have high enough operating frequency range as the moreexotic process like pHEMT or heterojunction bipolar transistor (HBT).The analog approach is often called regenerative injection-lockedfrequency divider (ILFD). Recently, there has been a lot of researchto use this technique with CMOS at much lower operating range.However, operating bandwidth is fairly narrow due to the nature ofthis architecture. In VCO design, one of the key parameters is VCOpulling. Basically, the VCO output frequency will be pulled away if acontinuous wave (CW) signal at a different frequency is nearby. VCOpulling is an undesired characteristic, but it is used cleverly to designthe ILFD. ILFD is built on this phenomenon by adding a feedbackloop, along with a mixer, oscillator or an amplifier with appropriatefeedback network and appropriate filters.Free download the full document athttp://rfdesign.com/mag/503rfdf1.pdf
CMOS Frequency Divider with Differential Injection Locking
The improvement of the performance of the frequencysynthesizer is indispensable for improving the performance ofRF transceiver circuits. A voltage-controlled oscillator (VCO)and a frequency divider (FD) operating at full speed for afrequency synthesizer are the key components of theimprovement of a performance. Recently, the VCO operatingwith a low supply voltage for the millimeter wave band hasbeen proposed . On the other hand, in the FD, it is difficultto realize low power and high speed simultaneously. Althougha high-speed FD using an LC resonator has been proposed inrecent years , the locking range of input is narrow and theconsumed chip area is large due to the use of inductors. It isnoted that a wide locking range for the FD is desirable in orderto ensure the operation margin of the whole system. Free download the full document athttp://hcac.hawaii.edu/tcwct03/papers/s10p04.pdf
Division of odd number
Frequency division by an odd number is also possible. The circuit to the left is a demonstration of a divide-by-3 counter. No gates are required to control the sequence if JK flip-flops are used; feeding the output signals back to the appropriate inputs is sufficient. Of course, it is not possible to get a symmetrical (50% duty cycle) square wave with this circuit. The A output is at logic 1 for two clock pulses out of three; the B output is at logic 1 for one clock pulse out of three. Thus, duty cycles of 1/3 (33.333%) and 2/3 (66.667%) are available. Free download the full document athttp://www.play-hookey.com/digital/frequency_dividers.html
Digital dividers>
To divide a digital signal by an integer multiple a Johnson counter is used. This is a type of shift register network that is clocked by the input signal. The last register’s complemented output is fed back to the first register’s input. The output signal is derived from the combination of the register outputs. For example, a divide-by-3 divider can be constructed with a 3-register Johnson counter. The three valid values for each register are 000, 100, 110, 111, 011, and 001. This pattern repeats each time the network is clocked by the input signal. The values 000 and 111 occur three clock pulses apart and control the state change of the output signal. Additional registers can be added to provide additional integer divisors.For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal. The least-significant output bit alternates at the same rate as the input, the next bit is the 1/2 the rate, the third bit is 1/4 the rate, etc. An arrangement of flip-flops are a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations including temperature. The easiest configuration is a series where each flip-flop is a divide-by-2. For a series of three of these, such system would be a divide-by-8. By adding additional logic gates to the chain of flip flops, other division ratios can be obtained. Integrated circuit logic families can provide a single chip solution for some common division ratios.
Fractional-n dividers
A fractional-n frequency synthesizer can be constructed using two integer dividers, a divide-by-n and a divide-by-(n + 1) frequency divider. With a modulus controller, n is toggled between the two values so that the VCO alternates between one locked frequency and the other. The VCO stabilizes at a frequency that is the time average of the two locked frequencies. By varying the percentage of time the frequency divider spends at the two divider values, the frequency of the locked VCO can be selected with very fine granularity. Introduction In the wireless communication market, trends are moving towards smaller size, fewer parts, longer lifetime and higher frequency operation. These trends imply that wireless communications circuits must incorporate higher integration and that their design and IC technology must be optimized for low power and high frequency system. One innovative method to increase the frequency of programmable divider is discussed. The new method not only increases the frequency of operation but also decreases circuit complexity and power dissipation. This new design use synchronous counters instead of asynchronous counters. The digital gates are optimized for minimum propagation delay and loading effect using progressive sizing of the transistors. This is better configuration in every aspect in terms of frequency, power dissipation and chip area. The scaling of CMOS technologies to deep submicron has made CMOS a technological option for the low-gigahertz frequency range. However, for CMOS to become a commercial option for RF building blocks requires compliance to all trends of the consumer market: miniaturization, low cost, high reliability and long battery lifetime. Bulk CMOS technologies presently available satisfy the low cost and reliability trends by standard design practice. Complying with miniaturization and long battery lifetime, on the other hand, demands CMOS building blocks with low-power dissipation and good electromagnetic compatibility (EMC) characteristics. A critical RF function in this context is the frequency synthesizer, more particularly the programmable frequency divider. The divider consists of logic gates Which operate at RF frequency, Due to the divider’s complexity, high operation frequency normally leads to high power dissipation. Other crucial aspects of the present-day consumer electronics industry are the short time available for the introduction of new products in the market, and the short product lifetime. On top of that, the lifespan of a given CMOS technology is also short, due to the aggressive scaling of minimum feature sizes. Short time-to-market demands architectures providing easy optimization of power dissipation, fast design time and simple layout work. High reusability, in turn, requires an architecture, which provides easy adaptation of the input frequency range and of the maximum and minimum division ratios of existing designs. The choice of the divider architecture is therefore essential for achieving low-power dissipation, high design flexibility and high reusability of existing building blocks. The divider can be implemented using static or dynamic cmos circuits. Dynamic circuit techniques evolved in the last few years into several cmos circuit technique such as domino, NORA, TSPC circuits. Nevertheless, the field of CMOS integrated circuits has reached a level of maturity, where it is now mainstream technology for higher integration density, low power consumption. Therefore, we had chosen cmos to design the programmable divider. The designed dividers have increased frequency capability with reduction of propagation delay using synchronous counters instead of asynchronous counters. visit http://www.suchitav.com for download articles
Design
frequency divider is an important building block in today’s TRFIC and microwave circuits because it is an integral part of the phase-locked loop (PLL) circuit. In a typical PLL loop, the output of the voltage-controlled oscillator (VCO) is divided down by the frequency divider to a frequency the temperature-compensated crystal oscillator (TCXO) operates (typically from 10 MHz to 30 MHz). The divided signal and TCXO are fed into the phase detector for comparison. The output phase difference is used to adjust the VCO output frequency. The frequency divider is also widely used to generate a precision I/Q signal if the input signal has a 50% duty cycle, for the modern in-phase and quadrature (I/Q) modulator or demodulator. For the signal with duty cycle other than 50%, an additional divideby- 2 can be used to generate the 50% duty cycle. Compared with the traditional resistor and capacitor (RC) quadrature generation, the frequency divider approach is easier to implement, is lower power and offers smaller phase imbalance. Digital logic approaches Since the PLL is part of the RF circuit, one would think the frequency divider should be analyzed by the analog circuit theory. But it turns out the most widely used approach is based on the digital logic gate. The RF analog engineer typically puts on the digital logic hat for a minute when analyzing the frequency divider. It will be much easier to understand and analyze the digital approach in the digital domain and the analog approach in the analog domain. Within the digital domain, the design strategy can be further divided into two categories: static logic and dynamic logic. The static implementation is the most popular approach. The memory cell is a true bistable circuit, unlike the parasitic capacitor used in the dynamic approach. One standard design is the divider by 2 cell shown in Figure 1. In today’s design software, it is treated as a standard digital cell. There are many names for circuits similar to Figure 1, such as a Johnson divider, toggle switch, complementary metal oxide semiconductor (CMOS) prescaler, emitter couple logic (ECL) and a source couple logic (SCL). When it is implemented in CMOS, it is called SCL. When it is implemented in a bipolar process, it is logically called ECL. For this illustration, CMOS implementation (SCL) is used. Free download the full document at http://rfdesign.com/mag/503rfdf1.pdf Analog approach The frequency divider with analog approach is also widely used. It tends to be used in the very high frequency millimeter wave range, anywhere from 20 GHz up to 100 GHz. Also, they tend to be in discrete form. The reason for this is the CMOS or BiCMOS process still doesn’t have high enough operating frequency range as the more exotic process like pHEMT or heterojunction bipolar transistor (HBT). The analog approach is often called regenerative injection-locked frequency divider (ILFD). Recently, there has been a lot of research to use this technique with CMOS at much lower operating range. However, operating bandwidth is fairly narrow due to the nature of this architecture. In VCO design, one of the key parameters is VCO pulling. Basically, the VCO output frequency will be pulled away if a continuous wave (CW) signal at a different frequency is nearby. VCO pulling is an undesired characteristic, but it is used cleverly to design the ILFD. ILFD is built on this phenomenon by adding a feedback loop, along with a mixer, oscillator or an amplifier with appropriate feedback network and appropriate filters. Free download the full document at http://rfdesign.com/mag/503rfdf1.pdf
CMOS Frequency Divider with Differential Injection Locking
The improvement of the performance of the frequency synthesizer is indispensable for improving the performance of RF transceiver circuits. A voltage-controlled oscillator (VCO) and a frequency divider (FD) operating at full speed for a frequency synthesizer are the key components of the improvement of a performance. Recently, the VCO operating with a low supply voltage for the millimeter wave band has been proposed . On the other hand, in the FD, it is difficult to realize low power and high speed simultaneously. Although a high-speed FD using an LC resonator has been proposed in recent years , the locking range of input is narrow and the consumed chip area is large due to the use of inductors. It is noted that a wide locking range for the FD is desirable in order to ensure the operation margin of the whole system. Free download the full document at http://hcac.hawaii.edu/tcwct03/papers/s10p04.pdf
Division of odd number
Frequency division by an odd number is also possible. The circuit to the left is a demonstration of a divide-by-3 counter. No gates are required to control the sequence if JK flip-flops are used; feeding the output signals back to the appropriate inputs is sufficient. Of course, it is not possible to get a symmetrical (50% duty cycle) square wave with this circuit. The A output is at logic 1 for two clock pulses out of three; the B output is at logic 1 for one clock pulse out of three. Thus, duty cycles of 1/3 (33.333%) and 2/3 (66.667%) are available. Free download the full document at http://www.play-hookey.com/digital/frequency_dividers.html