Design Guidlines on PCB layout



• Use multi-layer PCBs that provide separate VCC and ground planes.
• Add 10 to 30 ohm resistors in series to each of the switching outputs to limit the current flow into
each of the outputs.
• Create synchronous designs that will not be affected by momentarily switching pins.
• Assign I/O pins to minimize local bunching of output pins.
• Place the power and ground pins next to each other. The total inductance will be reduced by mutual
inductance, since current flows in opposite directions in power and ground pins.
• Use a bigger via size to connect the capacitor pad to the power and ground plane to minimize the
inductance in decoupling capacitors.
• Use surface mount capacitors to minimize the lead inductance.
• Use low effective series resistance (ESR) capacitors. The ESR should be < 400 ohm. • Each GND pin/via should be connected to the ground plane individually. • To add extra capacitance on the board, It is recommended to place a ground plane next to each power (VCC) plane. This placement gives zero lead inductance and no ESR. The dielectric thickness between the two planes should be ~5 mils. • Place suitable termination resistor to ensure impedance matching between the line impedance (R O )and the terminating resistor (R T ) is equal to the line impedance. • Use a ground plane next to the PLL power supply plane to reduce power-generated noise. • Place analog and digital components only over their respective ground planes. • Use ferrite beads to isolate the PLL power supply from digital power supply. • Add the recommended decoupling capacitors for as many VCC/GND pairs as possible. • Place the decoupling capacitors as close as possible to the power and ground pins of the device. • Add external buffers at the output of a counter to minimize the loading on silicon device pins. • Configure the unused I/O pin as an output pin and then drive the output low. This configuration acts as a virtual ground. Connect this low driving output pin to GNDINT and/or the boards ground plane. • Limit load capacitance by buffering loads with an external device, or by reducing the number of devices that drive the bus. • Eliminate sockets whenever possible. • Reduce the number of outputs that can switch simultaneously and/or distribute them evenly throughout the device. • Move switching outputs close to a package ground pin. • Create a programmable ground next to switching pins. • Eliminate pull-up resistors or use pull-down resistors. • Connect the capacitor pad to the power and ground plane with larger via to minimize the inductance in decoupling capacitors and allow for maximum current flow. • Use wide, short traces between the via and capacitor pads, or place the via adjacent to the capacitor pad. • Traces stretching from power pins to a power plane (or island, or a decoupling capacitor) should be as wide and as short as possible. This reduces series inductance, and therefore, reduces transient voltage drops from the power plane to the power pin. Thus, reducing the possibility of ground bounce. • Use surface-mount low effective series resistance (ESR) capacitors to minimize the lead inductance. The capacitors should have an ESR value as small as possible. • Connect each ground pin or via to the ground plane individually. A daisy chain connection to the ground pins shares the ground path, which increases the return current loop and thus inductance. • For equal power distribution, use separate power planes for the analog (PLL) power supply. Avoid using trace or multiple signal layers to route the PLL power supply. • Turn on the slow slew rate logic option when speed is not critical. • Eliminate sockets whenever possible. • Depending on the problem, move switching outputs close to either a package ground or VCC pin. Eliminate pull-up resistors, or use pull-down resistors. • Use multi-layer PCBs that provide separate VCC and ground planes to utilize the intrinsic capacitance of GND-VCC plane. • Create synchronous designs that are not affected by momentarily switching pins. • Add the recommended de-coupling capacitors to VCC/GND pairs. • Place the decoupling capacitors as close as possible to the power and ground pins of the device. • Do not use via in clock transmission lines. Via can cause impedance change and reflection. • Place a ground plane next to the outer layer to minimize noise. If you use an inner layer to route the clock trace, sandwich the layer between reference planes. • Terminate clock signals to minimize reflection. • Use point-to-point clock traces as much as possible. • Configure unused I/O pins as output pins, and drive the output low to reduce ground bounce. This configuration will act as a virtual ground. • Configure the unused I/O pins as output, and drive high to prevent VCC sag. • Widen spacing between signal lines as much as routing restrictions will allow. Try not to bring traces closer than three times the dielectric height. • Design the transmission line so that the conductor is as close to the ground plane as possible. This technique will couple the transmission line tightly to the ground plane and help decouple it from adjacent signals. • Use differential routing techniques where possible, especially for critical nets (such as, match the lengths as well as the gyrations that each trace goes through). • If there is significant coupling, route single-ended signals on different layers orthogonal to each other. • Minimize parallel run lengths between single-ended signals. Route with short parallel sections and minimize long, coupled sections between nets. • Keep clock traces as straight as possible. Use arc-shaped traces instead of right-angle bends. • Do not use multiple signal layers for clock signals.