capacitor in DRAM
embedded DRAM technology for system-on-chip devices (SoCs) reduces the cell capacitance to 5fF, one-third its previous value, yet maintains the performance of logic circuits. Speed is 322MHz, data storage power is 60µW, and circuit noise is extensively reduced to allow the DRAM to operate with the low cell capacitance.
Differences between the processes used to produce DRAM and logic LSIs typically cause problems when DRAM is incorporated into a system-on-chip (SoC) device. The DRAM memory cell — a cell-access transistor and a cell capacitor — stores the data value (1 or 0) as a charge on the cell capacitor. Traditionally, high-temperature processing has been used to form the cell capacitor (figure 1), but this processing deteriorated the performance of the logic circuit cores in the SoC. “The ability to coexist with logic circuits is a very important factor for embedded DRAM,” said Mr. Yamazaki.
An embedded DRAM technology jointly developed by Renesas and Matsushita Electric Industrial eliminates the need for high-temperature processing by positioning the cell capacitor under the bit line and using a metal-insulator-metal (MIM) structure for the two metallic capacitor electrodes (figure 1). Therefore, no damage occurs to the logic circuit cores, which have the same performance as those produced by a logic LSI manufacturing process.
To achieve high speed and lower power consumption, the new technology reduces the capacitance of the DRAM cell capacitor to 5fF, less than one-third the previous value. A new bit-line noise-suppression technology and a high-precision bit-line precharge-potential adjustment technology enable stable operation with the low cell capacitance.
The charge on the cell capacitor is transferred to the bit-line pair via the cell-access transistor. A precharge transistor and an equalizer transistor are connected to the bit line pair. In the past, both transistors were NMOS FETs. When they were turned on, their combined capacitance generated overlapping noise and significantly reduced the potential of the bit line (diagram on left in figure 2). In the new circuit, though, the equalizer transistor has been changed to a PMOS FET and separated from the precharge transistor (diagram on right in figure 2). Because the noise due to the parasitic capacitance of the PMOS FET is opposite in polarity to that of the NMOS FET, the two noise voltages cancel each other out.