calibre tutorial

NOTE: For Calibre DRC and LVS to properly check your layout, you must have only SHAPE (and not SYM) pins defined in your layout. These must be created using the pin (pn) metal layers, rather than the drawing (dg) layers.
DRC
Although designers might be conscious of the design rules when performing the layout, there is a possibility of overlooking and thus violating the design rules. So, DRC (design rule checking) is a step taken to alert us of any violations. This step is important because the violation of any design rules would result in a higher probability, and in some cases an absolute certainty, that the fabricated chip does not work as desired. To reduce the amount of clutter in your home directory, first create a directory here called “calibre_drc”. This is where all the files required and produced by Calibre DRC will be stored. Calibre DRC operates by first streaming out the layout from Cadence. Therefore, the stream out options must be set correctly. From the CIW window, choose File -> Export -> Stream. This opens the “Virtuoso Stream Out” form. Hit the “User-Defined Data” button, opening the “Stream Out User-Defined Data” form. In the “Layer Map Table” field, enterrfic/tech/tsmc013/gds2/opus.map
In the “Pin Text Map Table” field, enter
rfic/tech/tsmc013/gds2/pinText.map
Then make sure that the the “Convert Pin to” button directly above is set to “text”. When this is complete, hit OK. The Stream Out form will be shown again.
In the Stream Out form, select the layout you wish to stream out by pressing the “Library Brower” button. This will bring up the Library Manager and allow you to choose the appropriate layout. The form will be filled in with the correct data.
In the “Output File” field, enter the name of the stream file you wish to create. Make sure the file will be created in your “calibre_drc” directory. An example is:
./calibre_drc/layout1.gds
The remaining options in the form can be set to their defaults.
Hit OK in the Stream Out form. After a short period, Cadence will produce a message indicating that the layout has been streamed out successfully. Note that warning messages can (usually) be ignored. In addition, after you have streamed out the file for the current layout, you do not need to do it again; Calibre DRC (or LVS) will do it for you whenever it is run.
From the layout window, choose Calibre -> Run DRC. If Calibre prompts for a Runset file, just hit Cancel. You will then see a series of buttons to set up the Rules, Inputs, Outputs, and Run Control for Calibre DRC.
Select the “Rules” button. In the “Calibre-DRC Rules File” field, enter:
rfic/tech/tsmc013/calibre/DRC/calibre_prelaygen.rul
In the “Calibre-DRC Run Directory” field, enter the path to your “calibre_drc” directory.
Select the “Inputs” button. Make the sure the “Primary Cell” field contains the name of your layout. Also ensure that the file format is GDSII and that the “Export from layout viewer” box is highlighted. The name of the stream out file will be shown in the “Files” field. You can change the name if you wish.
Select the “Outputs” button. Make sure that the “Start RVE after DRC finishes” box is highlighted. RVE is the interface used to view the DRC results. The other displayed options can be set to their defaults.
Hit “Run DRC”. You can overwrite the files from previous DRC runs when prompted. While DRC is running, you will be shown the transcript file that is being produced.
Once DRC has finished running, the RVE window will be displayed. A list of all the DRC errors in each cell of your layout will be shown here in a tree format. You can expand the tree and view each error separately. Double-clicking on an error number will have Cadence show you the location of the error in your layout. Also, right-clicking on the error number will enable you to highlight the error directly on your layout. Correct the errors and run DRC again to re-check your layout.
After running DRC, you will likely receive polysilicon density and metal density errors for each layer of metal. You can ignore these for purposes of this course.
LVS
As was done for DRC, create a directory called “calibre_lvs” in your root directory. This is where all the files required and produced by Calibre LVS will be stored
If you have not already done so, set up Cadence to stream out the layout you wish to check (see the appropriate steps in setting up DRC above).
From the layout window, choose Calibre -> Run LVS. You will then see a series of buttons to set up the Rules, Inputs, Outputs, and Run Control for Calibre LVS.
Select the “Rules” button. In the “Calibre-LVS Rules File” field, enter
rfic/tech/tsmc013/calibre/LVS/calibre.rul
In the “Calibre-LVS Run Directory” field, enter the path to your “calibre_lvs” directory.
Select the “Inputs” button. Then select the “Layout” tab. Make sure the “Primary Cell” field contains the name of your layout. Also ensure that the file format is GDSII and that the “Export from layout viewer” box is highlighted. The other displayed options can be set to their defaults.
Select the “Netlist” tab. Ensure that the “Primary Cell” field contains the name of the schematic you wish to compare. Also make sure that the file format is SPICE and that the “Export from schematic viewer” box is highlighted. The other displayed options can be set to their defaults.
Select the “Outputs” button. Make sure that the “Start RVE after LVS finishes” box is highlighted.
Hit “Run LVS”. While LVS is running, you will be shown the transcript file that is being produced.
Once LVS has finished running, the RVE window will be displayed. A list of all LVS mismatches will be shown here in a tree format. As with Calibre DRC, you can expand the tree and view each mismatch separately. Correct the mismatches and run LVS again to re-check your layout and schematic.

Typical steps to do this Calibre

Running Calibre
DRC

Copy the rule file to a location of
your local directory or point to your rule file
(for example $rfic-design/ ).
Insert "PORT LAYER POLYGON 2 3" into line 50 of your local "ami05.rules"
file.
Then translate your layout into GDSII format (a standard layout format
widely used in industries). To do this:
Run $ adk_ic &
Then open your layout, for example, nand2.
In the IC Station menu bar, click Translate > Write GDSII.
Type "nand2.GDSII" as the Output GDS File. (The file will be located at $rfic-design/nand2.GDSII)
Click "Write Options …."
Tick Replace Existing GDSII Stream FIle.
Click OK. Click OK.
You may now use "Translate > Read GDSII" to see if your layout is translated
successfully.
Open a new xterm and then connect to moss or lichen.
$ runmgc
Then choose c and then choose y.
$ calibre -gui &
The Calibre Interactive window with 4 buttons (DRC, LVS, PEX, RVE) will
appear.
Click DRC.
The Calibre Interactive DRC window will appear.
Click Cancel to the Load Runset File window.
(You could load your runset file if this is not your first run.)
In the Rules button, choose your local
"ami05.rules" file as the Calibre-DRC Rules File.
Choose a directory which is empty as the Calibre-DRC Run Directory.
(You may go to xterm and use mkdir to create a new directory before
this step.)
Click the Inputs button.
Choose nand2.GDSII as your layout file.
Choose GDSII as the File Format.
Type nand2 as the Primary Cell.
Click Flat at the top of the window.
Click Run DRC button.
Your should have no errors with the DRC results since the layout should have
passed DRC
in IC Station.
You may save your runset file for future re-use.

Running Calibre
LVS

Translate your schematic which is designed by using Design Architect
into SPICE netlist format. To do this:
Start Design Architect-IC ($ adk_daic &).
(You can have two xterm s: One for "runmgc > i > a" to be used to
run adk_daic.
The other is "runmgc > c > y" to be used to run calibre -gui)
Click "File > Export SPICE" on the menu bar of Design Architect-IC.
Output Type: LVS
Output Names in What Case: Lower
Design Path: <the path of your schematic, for example, $rfic-design/nand2>
Options: Yes
Tick "Wrap Netlist in .subckt ?"
Output File: $rfic-design/nand2.sch.net
Click OK.
You could use any text editor to see the generated netlist.
Click LVS on the Calibre Interactive window (invoked from: $ calibre
-gui &).
Calibre Interactive LVS window will appear.
Click Cancel to the Load Runset File window.
(You could load your runset file if this is not your first run.)
In the Rules button, choose your local
"ami05.rules" file as the Calibre-LVS Rules File.
Choose a directory which is empty as the Calibre-LVS Run Directory.
(You may go to xterm and use mkdir to create a new directory before
this step.)
Click the Inputs button.
Choose Flat.
Choose Layout vs Netlist (default).
In the Layout Tab, choose "nand2.GDSII" as the layout file
(The GDSII file is generated by the Running Calibre-DRC steps above).
You may use the button […] to browse your directory.
File Format: GDSII
Primary Cell: nand2
In the Netlist Tab, choose "nand2.sch.net".
File Format: SPICE
Primary Cell: nand2
Click Run LVS.
Calibre LVS RVE window will appear. You can use it to find out why the
netlists do not match.
Since LVS check has been done in IC Station for your design, you should have
your LVS results correct.
You may save your runset file for future re-use.

Running Calibre
PEX

Click PEX on the Calibre Interactive window (invoked from: $ calibre
-gui &).
Calibre Interactive PEX window will appear.
(PEX means Parasitics EXtraction)
Click Cancel to the Load Runset File window.
(You could load your runset file if this is not your first run.)
In the Rules button:
Calibre-PEX Rules File: <your local "ami05.rules" file>
Choose a directory which is empty as the Calibre-PEX Run Directory.
(You may go to xterm and use mkdir to create a new directory before
this step.)
Click the Inputs button.
In the Layout Tab, choose "nand2.GDSII" as the layout file.
You may use the button […] to browse your directory.
File Format: GDSII
Primary Cell: nand2
In the Netlist Tab, choose "nand2.sch.net".
File Format: SPICE
Primary Cell: nand2
Click the Outputs
button.
Extraction Type: Transistor Level, and C (Lumped C +
coupling caps)
(We have difficulties running RCC and RC now.)
In the Netlist Tab,
Format: ELDO
Use Names From: SOURCE
File: nand2.ELDO.net
Click the Run Control button.
Un-tick "Run hierarchical version of Calibre-LVS."
Click the Run PEX.
The layout netlist with parasitic capacitance is generated.
You may save your runset file for future re-use.

Post-layout Simulations

Start da_ic again. Go to File > Model Registration > Create.
In the new window, choose ELDOSPICE as Model Type, and click
on Choose File to find the SPICE model files. We will use the
nand2 lumped extraction as an example. So choose nand2.sch.net file.
The Model Registration program will know that the netlist is associated with
the nand2 component.
Type in a new name for the symbol associated with the model, say
nand2_postsim, click on Add new next to it, and click on Symbol Layout
Properties. Choose a corresponding pin direction and placement for the
inputs/outputs. Change the shape if you want. Click ok to close the window. If
you click on open symbol, you can see how the new symbol will look like.
Click on register to finish the registration.
At this point, if you don t want to change your first test bench, make a
copy of it using design manager.
Open the test bench. Delete the "old" symbol for your nand2 gate.
When you insert the new instance, make sure you navigate into the nand2
directory and choose the newly created symbol.
Connect up the Power and GND nodes and you can simulate the schematics as
before, but this time, you should take a look at the generated netlist. It
will use the SPICE model of the lumped netlist generated by Calibre-PEX,
instead of the schematics for the nand2 gate.