cadence assura tutorial
Writing Assura Layer Definition and Derivation Rules
Original Layers versus Derived Layers
Deriving Layers
- Layout Shapes
- Polygon and Edge Data Formats
- Conics and Paths
- Converting Polygons to Edges
- Logical Operations and Edge Layers
Invalid Graphics Data
Outputting Layers
Generating Layers for Area Fill
- Background on Area Fill
- generateFill Versus generateRectangle and generateCustomFill
- Comparison of generateFill and generateRectangle/generateCustomFill
- Controlling Fill Cell Naming
3
Writing Assura Design Rule Check (DRC) Rules
- Assura DRC Methodologies
- Limiting Design Rule Checking to Specific Areas
- verifyArea
- Assura Area-Based DRC
- DRC Rule Writing Tips
4
Writing Assura LVS Device Extraction Rules
Overview of the Device Extraction Rule File
Deriving Device Recognition Layers
- Creating Unique Device Recognition Regions
- Deciding Which Recognition Region to Use
- Deriving Device Terminal Layers
- Deriving Contact Layers
Extracting Cells as Black Box Cells
- Defining Black Box Cell Pins
- Defining Devices as Black Box Devices
- Defining Interconnect Layers within Black Box Cells
- Creating Device Parameters with SKILL Functions
- Extracting Device Parameters from CDF for DFII Layouts
5
Netlisting from the Schematic
- Netlisting Standard and Generic Devices
- Creating a dfIIToVldb Rule File
- Invoking the dfIIToVldb Netlister
- Obtaining Custom Device Properties
- Netlisting Multiplied Instances
Preparing Verilog Netlists for Assura LVS
Reading Mixed Format Netlists
- CDL Instances in DFII Schematics
- Verilog Instances in DFII Schematics
- DFII Instances in Verilog Modules
- CDL Instances in Verilog Modules
Translating CDL or SPICE Netlists to Assura Format
6
Assura LVS Comparison Rules
Compare Rules Overview
Representing Cell and Device Names
Processing Generic or Custom Devices
Specifying Cell Correspondence by Name
- A Closer Look at Name Binding
- How to Specify a Binding File
- Binding File Syntax
- Cell Names in the Binding File
- Using Wildcards in Bindings
- Specifying Device Bindings
- Multiple Bindings
- Automatic Binding of Assura Variant Cells
7
Assura RCX and Capgen Setup
Capacitance and Resistance Extraction Settings Table
Step 1. Establish an RCX Technology Directory
Step 2. Create a Process Description File
Step 3. Convert LVS Extraction Rules
Step 4. Create a p2lvsfile Mapping File
- How RCX Treats Unmapped Metal and Contact Layers.
- Substrate Mapping in the p2lvsfile
- Creating the p2lvsfile:
- Stamping in RCX
Step 6. Capgen Compilation and Script Initialization
How Assura RCX Uses the Capgen Setup Files
Step 7. Run Subgen for Substrate Profile (Optional)
Assura RCX Setup Steps Output Files
8
Setting Up Technology Data
Introduction
Overview of the Technology Directory and Rule Sets
Running Assura Tools with the Technology Directory
Setting Up and Using Technologies
Using the Assura GUI to Create Rule Sets
Glossary
9
Defining GUI Templates for Users
Presetting DRC and LVS Run-time Options
- avCompareRules List
- How to Set avCompareRule Options
- General avCompareRules and Options
- Network-Specific avCompareRules and Options
Presetting the RCX Extraction Options
Setup Tab
Extraction Tab
Filtering Options Tab
Netlisting Options Tab
Run Details Tab