BJT matching

my ckt has two bjts. in that one has m:1 and another has m:8. so i placed the bjts in a matched pair.one in center and remaing 8 are placed around it.like below
X X X
X O X
X X X
i have placed 9 bjts in a 3*3 matrix form.and i give corresponding inputs to bjts and then run LVS. it shows a error, that the formed device was “MAL formed device”. i am unable to solve the problem. please send me the above error correction procedure and also the netlist for bjt.
the transistor was VPNP in tsmc130nm technology
it is so urgent.thanks
Re: BJT matching
Hi,
the “mal formed device” error explains
the extraction step can not build the device terminals because
they were not drawn correctly or some terminal for the device is missing
hope this point helps you to correct the error
1. check the lvs netlist , whether it is showing 8 bjts or something else,
guru
Re: BJT matching
All the terminals and connections are correct. I found that LVS clean when all the BJTs are seperated by 0.31u. what is the need to provide space between two p-implants. when two are combined there is no problem. but why it asks for 0.31 space.
ANOTHER PROBLEM:
HOW TO DEFINE DUMMY POLY RESISTORS IN SPICE NETLIST. I AM USING TSMC 130nm tecnology.i.e. “rphpoly”.
Re: BJT matching
Hi,
it is great you solved the problem, congratulation,
little bit tuning required for further improvement
You can see the layers for dummy in the technology file
it may be
RWDMY dummy layer to form N-Well resistor
RPDMY dummy layer to form OD/POLY resistor
RMDMY dummy layer to form METAL resistor
put the layer according to your design on the top for specifying dummy
0.31um is like this defined in the technology file, if your design is less than 0.31um it might short after fabrication