asic interview 1
application specific integrated circuit interview questions and answers
1) Why are PMOS transistor networks generally used to produce high (i.e. 1)signals, while NMOS networks are used to product low (0) signals?
PMOS is used to drive ‘high’ because of the threshold voltage-effectThe same is true for NMOS to drive ‘low’.A NMOS device cant drive a full ‘1’ and PMOS cant drive full ‘0’
Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS gives you a defined rail to rail swing
2) On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean?
The numbers you see there are usually the width and the length of the devices (channel dimensions drawn in the layout)If given only one number it’s the width combined with a default length
3) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?
To limit the height of the stack.
As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be.
4) What is meant by static and dynamic power with respect to the operation of a CMOS gate?
Why do CMOS gates dissipate close to zero static power?
Why is the static power not exactly zero?
Cool What is a transmission gate, and what is it used for typically?
Why are transmission gates made with both PMOS and NMOS transistors?
9) What are the major factors that determine the speed that a logic signal propagates from the input of one gate to the input of the next driven gate in the signal’s path?
10) What are some of the major techniques that are usually considered when one wants to speed up the propagation speed of a signal?
11) What is the difference between a mask layer and a drawn layer in an IC layout?
Why do layout designers usually only specify drawn layers?
12) In an IC layout, what is a polygon and what is a path?
What are the advantages and disadvantages of each?
A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped, however, it’s off grid with 45 degree angle. Polygon is always on-grid, unless it’s a copy and flip. However, polygon is hard to edit and work with.
13) What is the difference between a contact and a via?
What is a “stacked” via process?
Via: a contact between two conductive layers.
Contact:Opening in an insulating film to allow contact to an underlying electronic device.
The placement of vias directly over the contacts or other,lower vias is known as stacked via.
14) Why is it that NMOS transistors can be created directly in a P-type substrate, whereas PMOS transistors must be created in an N-type well?
15) Why must transistors be provided with “bulk” connections?
What voltage levels are connected to a p-type substrate and an n-type well through these connections, and why?
To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit
16) What are process design rules?
What is their major purpose?
How are design rules created?
17) What are width rules, space rules, and overlap rules?
18) What is a “vertical connection diagram”?
What is it used for?
vertical connection diagram illustrates the relative position, going vertically, of all the drawn layers. Such diagrams are especially useful in complex processses, such as DRAM processes.
19) The routing strategies for the power grid and global signals are usually defined at the start of planning a new chip floorplan. Why?
20) What are the major advantages of hierarchical IC design?
Concurrent design
• Design reuse
• Predictable schedules