and gate verilog model



module V_and(in,out);
input [0:size-1] in;
output out;
voltage in,out;
parameter real size = 2 from [2:inf),
vout_high = 5,
vout_low = 0 from (-inf:vout_high),
vth = 1.4,
tdelay = 5n from [0:inf),
trise = 1n from [0:inf),
tfall = 1n from [0:inf);
integer in_state[0:size-1];
integer out_state;
real vout;
analog
begin
@(initial_step)
for(i=0;i vth;
out_state = 1;
for (i=0;i