A 1.2-V 250-mW 14-b 100-MS s digitally calibrated pipeline ADC in 90-nm CMOS
FREE-DOWNLOAD H Van de Vel, BAJ Buter… – Solid-State Circuits, …, 2009
Abstract—This paper describes a digitally calibrated pipeline analog-to-digital converter
(ADC) implemented in 90 nm CMOS technology with a 1.2 V supply voltage. A digital background
cal- ibration algorithm reduces the linearity requirements in the first stage of the pipeline